Bases de datos bibliográficas:

Publicaciones del académico:

• Comprehensive RTL-to-GDSII Workflow for Custom Embedded FPGA Architectures Using Open-Source Tools
• Design and Hardware Implementation of a Highly Flexible PRNG System for NIST-Validated Pseudorandom Sequences
• Cachedia: An Environment for Efficient Cache Verification with Graphic Visualization for Debugging
• Diseño del layout de una unidad aritmeticológica utilizando the electric
• When AI Turns Malicious: Unethical Use of LLMs for Hardware Design
• Diseño del layout de una unidad aritmeticológica utilizando the electric
• Diseño del layout de una unidad aritmeticológica utilizando the electric

• Neurona de Impulsos Adaptación en Frecuencia Con Modificación en Impulsos
• Propuesta de una Metodología para Implementar Controladores en Metalenguaje
• Implementación del método de Runge-Kutta en HDL
• Pseudorandom Number Generator Using a Chaotic System
• Development of an Embedded System for the Analysis and Testing of Gasoline Injectors
• Exploring New Approach With Open Source EDA Tools
• Proposal for PRNG System to Produce Pseudorandom Sequences
• Metodología Para Validación de Generadores Tipo PRNG Con Las Pruebas Estadísticas Del NIST
• Propuesta de un modelo para el ciclo de vida para una neurona de impulso
• Multiplicador de números enteros de 8 bits mediante sumas sucesivas
• Design of a New Neuro-generator with Neuronal Module to Produce Pseudorandom and Perfectly Pseudorandom Sequences
• Design of a New Neuro-Generator with a Neuronal Module to Produce Pseudorandom and Perfectly Pseudorandom Sequences

• Vector Accelerator Unit for Caravel
• ForEmb: A Forth-Inspired, Real-Time Interpreter for Embedded Systems

• Implementation of 8-Channel Pulse Width Modulation with AXI4-Lite Interface
• Design and Implementation in FPGA a Random Number Generator of 10 bits validated by NIST Maurer’s “Universal Statistical” and Binary Matrix Rank tests
• Design and Implementation in FPGA a Random Number Generator of 10 bits validated by NIST Maurer’s “Universal Statistical” and Binary Matrix Rank tests
• Diseño de un convertidor digital-analógico con Tecnología CMOS, para Aplicaciones en Microelectrónica
• DISEÑO COMPORTAMENTAL DE NEURONAS DE IMPULSO EN HARDWARE RECONFIGURABLE BASADAS EN EL MODELO DE IZHIKEVICH (BEHAVIORAL DESIGN OF SPIKING NEURONS IN RECONFIGURABLE HARDWARE …
• SISTEMA DE MONITOREO EN TIEMPO REAL DEL PESO APLICADO A MUELLES DE BALLESTA AUTOMOTRIZ (REAL-TIME MONITORING SYSTEM FOR WEIGHT APPLIED TO AUTOMOTIVE CROSSBOW SPRINGS)
• Diseño de un convertidor digital-analógico con Tecnología CMOS, para Aplicaciones en Microelectrónica
• Diseño de un convertidor digital-analógico con Tecnología CMOS, para Aplicaciones en Microelectrónica
• Design and Implementation in FPGA a Random Number Generator of 10 bits validated by NIST Maurer’s “Universal Statistical” and Binary Matrix Rank tests
• Design and Implementation in FPGA a Random Number Generator of 10 bits validated by NIST Maurer’s “Universal Statistical” and Binary Matrix Rank tests
• Design and Implementation in FPGA a Random Number Generator of 10 bits validated by NIST Maurer's 'Universal Statistical' and Binary Matrix Rank tests

• Nano transistores de efecto de campo tipo aleta para aplicaciones digitales
• Una revisión sistemática sobre el aprendizaje remoto de la matemática. Espirales

• Feedback rehabilitation system for children with problems of Spastic Hemiparesis in the upper extremities
• Sensing system with an artificial neural network based on floating-gate metal oxide semiconductor transistors
• IMPLEMENTACIÓN DEL SISTEMA HANUMAN EN MENSAJERÍA INSTANTÁNEA (HANUMAN SYSTEM IMPLEMENTATION ON INSTANT MESSENGER)

• 32-bit Microcontroller-Based Hardware-in-the-Loop Simulation for Controllers of Air-to-Fuel Ratio in Spark-Ignition Engines
• Low cost DSP-based educational embedded platform for real-time simulation and fast implementation of complex systems in Simulink
• Low cost DSP‐based educational embedded platform for real‐time simulation and fast implementation of complex systems in Simulink
• Statistical validation analysis between an experimental Shack-Hartmann aberrometer and a commercial device
• Low cost DSP‐based educational embedded platform for real‐time simulation and fast implementation of complex systems in Simulink
• Low cost DSP‐based educational embedded platform for real‐time simulation and fast implementation of complex systems in Simulink
• Low cost DSP‐based educational embedded platform for real‐time simulation and fast implementation of complex systems in Simulink

• Methodology to improve the model of series inductance in CMOS integrated inductors
• DESIGN AND IMPLEMENTATION ON A FPGA OF A FACIAL RECOGNITION SYSTEM USING “EIGEN FACES”
• MICROACELERÓMETRO MEMS, DISEÑO, ANÁLISIS ESTRUCTURAL Y ELECTROSTÁTICO (MEMS MICROACCELEROMETER, DESIGN, STRUCTURAL AND ELECTROSTATIC)
• DESIGN AND IMPLEMENTATION ON A FPGA OF A FACIAL RECOGNITION SYSTEM USING “EIGEN FACES”
• Implementación de un multiplicador de punto flotante de doble precisión basado en el estándar IEEE 754-2008
• Implementación de un multiplicador de punto flotante de doble precisión basado en el estándar IEEE 754-2008